Since the invention of the integrated circuit, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. A three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. In a typical formation process of 3D IC, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Through-substrate vias (TSV) are formed to interconnect devices on the first and second substrates. Other technologies for 3D IC exist too, such as Die-on-Wafer and Die-on-die. For Die-on-Wafer technology, electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dies are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dies may be added to the stacks before dicing. For Die-on-Die technology, electronic components are built on multiple dies, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding.
A 3D IC is a single chip. All components on the layers communicate with on-chip signaling, whether vertically or horizontally. Much higher device density has been achieved using 3D IC technology, and up to six layers of wafers have been bonded. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D IC technology has the potential of being the mainstream technology of the next generation.
Electrostatic discharge (ESD) is the sudden and momentary electric current that flows between two objects at different electrical potentials. The term is usually used to describe momentary unwanted currents that may cause damage to electronic equipment. ESD is a serious issue in integrated circuits, which can suffer permanent damage when subjected to high voltages.